The present invention relates to an inspecting method for a semiconductor device by which a plurality of integrated circuits of semiconductor chips formed on a semiconductor wafer are inspected at a time in the wafer state.
Advancement of electronic components mounting semiconductor integrated circuit devices (hereinafter referred to semiconductor devices) is remarkable in size reduction and price reduction in the past few years. With this advancement, the demand to size reduction and price reduction of semiconductor devices is further increasing.
According to a general mounting operation of semiconductor devices onto a printed circuit board, each semiconductor chip is electrically connected to a corresponding lead frame by means of a bonding wire, then the semiconductor chip and the lead frame thus connected are sealed by resin or ceramic before they are mounted on the printed circuit board. Meanwhile, the requirements to size reduction of electronic components made it possible to develop a novel mounting method of directly mounting electronic components on a printed circuit board when each semiconductor device is still in a semiconductor wafer state (hereinafter, the semiconductor device in this condition is referred to as "bare chip"). In view of introduction of such an advanced method, it will be significantly required to provide cheap and excellent bare chips whose quality are guaranteed.
To assure the quality of the bare chip, it is normally required to inspect each of semiconductor devices in the wafer state by a burn-in or the like. Performing one inspection to every single chip or minor group chips formed on a semiconductor wafer will take a long time to complete the inspection for all of numerous bare chips. Such an inspecting method is not practical to adopt in view of time and cost. Accordingly, there is an earnest need to the method capable of inspecting all the bare chips at a time in the wafer state by the burn-in or the like.
In the inspection of bare chips in the wafer state performed at a time, it is generally necessary to simultaneously apply a power voltage and a signal to each test electrode provided on each of plural semiconductor chips formed on one semiconductor wafer so as to operate all of the plural semiconductor chips. To this end, it will be necessary to prepare a probe card having extremely numerous (normally several thousands or more) probe needles each being brought into contact with a corresponding test electrode. However, a conventional needle type probe card cannot fulfill the task required in view of the number of pins and cost.
According to related proposals, there is known a contactor made of a thin probe comprising bumps formed on a flexible substrate (refer to Nitto Technical Bulletin, Vol.28, No.2, October 1990, PP.57-62).
Hereinafter, a burn-in using the above-described contactor will be explained in detail.
FIGS. 15(a) and 15(b) are cross-sectional views respectively showing a probing condition using the contactor. In FIGS. 15(a) and 15(b), reference numeral 100 represents a card type contactor. This contactor 100 comprises a polyimide substrate 101, a wiring layer 102 formed on the polyimide substrate 101, a bump 103 serving as a probe terminal, and a through hole wiring 104 connecting the wiring layer 102 and the bump 103.
As illustrated in FIG. 15(a), by pressing the contactor 100 against a semiconductor wafer 110 which is a substrate to be tested, a pad 111 formed on the semiconductor wafer 110 as a test electrode is electrically connected to the bump 103 of the contactor 100. If the temperature is maintained at the room temperature, the inspection will be successfully accomplished by simply applying a power voltage or a signal to the bump 103 through the wiring layer 102.
However, some of inspections in the atmosphere of high temperatures such as burn-in are conducted, heating up the semiconductor wafer 110 for temperature acceleration. FIG. 15(b) is a cross-sectional view showing a typical structural condition resulting from a heating operation to semiconductor wafer 110 wherein the temperature is increased from the room temperature, 25.degree. C., to 125.degree. C. In FIG. 15(b), the left half shows a central region of the semiconductor wafer 110, while the right half shows a peripheral region of the semiconductor wafer 110.
Polyimide constituting the polyimide substrate 101 has a larger thermal expansion coefficient than that of a silicon constituting the semiconductor wafer 110 (more specifically, the thermal expansion coefficient of silicon is 3.5.times.10.sup.-6 /.degree.C., while the thermal expansion coefficient of polyimide is 16.times.10.sup.-6 /.degree.C.). Due to this thermal expansion difference, the peripheral region of the semiconductor wafer 110 is subjected to a significant dislocation caused between bump 103 and pad 111. For example, it is now supposed that the semiconductor wafer 110 and the contactor 100 are aligned under the room temperature, and then they are heated up to 100.degree. C. As a result of this heating operation, 6 inches of semiconductor wafer 110 expands only 35 .mu.m whereas the contactor 100 expands 160 .mu.m. This means that the pad 111 and the bump 103 are dislocated from each other by 125 .mu.m in the peripheral region of the semiconductor wafer 110. For this reason, the peripheral region of semiconductor wafer 110 no longer maintains electrical connection between the pad 111 and the bump 103.
As explained in the foregoing description, according to the conventional inspecting method of a semiconductor device, the semiconductor wafer is inevitably subjected to high temperatures and the contactor being brought into contact with the semiconductor wafer is also subjected to high temperature. Due to the difference in thermal expansion coefficient between the semiconductor wafer and the contactor, there is caused so significant dislocation in the peripheral region of the semiconductor wafer that no electrical connection is maintained between the pad and the bump.